Letter
from the CEO
Welcome
to the April 2008 edition of the SRC Insider, a
newsletter designed to provide insight into SRC’s
product and software development.
Now, I know
what you’re thinking… that you haven’t heard from us in a
while. Am I right? Well, there’s a very good reason for that,
several in fact. Instead of doing a lot of talking, we’ve been
doing a lot of listening. Listening to our customers and
users about what they want and need. And now we're responding with
a whole lineup of new products in our SRC-7 family.
Series I MAP®
The Series I MAP combines the functionality of SNAP™ and MAP
into a single module with features that have been chosen to
primarily support streaming applications. It is also
the
only peer-connected reconfigurable processor utilizing a JEDEC
standard interconnect that can be used with either AMD or Intel
based commodity motherboards.
Available in three
MAPstation™ models starting at just $17,000, the Series I MAP provides
an economical implementation of SRC’s IMPLICIT+EXPLICIT™
Architecture. Read more about the Series I MAP
here.
iCarte™
Carte 3.1 will
support the Series I MAP as well as all other SRC products. But
for users who do not already have a Carte™ development license,
SRC has developed a new version of Carte, called iCarte,
which specifically supports the Series I MAP. iCarte is software
compatible with Carte and has the same look and feel.
Like the Series I MAP, iCarte has a very attractive price
point of only $5,000 for a perpetual license. Read
more about iCarte here.
New versions of the Series H
MAP
The five new versions of the Series H can be tailored to fit your
needs and price point. Read more about the new Series H
MAP offerings
here.
New
White Papers
SRC is publishing a series of SRC-7 white papers covering
such topics as edge detection, image processing, and SAR
backprojection among others. Read more
here. I think
you’ll be impressed by what you see!
Jon
Huppenthal
President & CEO
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Series
I MAP®
The
Functionality of SNAP™ and MAP in a Single Module
For some applications the SRC-7 Series H MAP is much more
feature-rich than is needed. In response to this, SRC has developed the Series I MAP. The Series I merges a single User Logic chip and a QDR on–board SRAM bank onto the SRC-7 SNAP module as shown in figure 1.
Series I MAP, Figure 1
This all-in-one module fits into a pair of interleaved DIMM slots on the microprocessor motherboard. Consequently, the Series I MAP does not consume a microprocessor socket and can actually double the memory bus bandwidth. This is best explained by the following figure.
Series I MAP Block Diagram. Figure 2
Figure 2 is a block diagram of the Series I MAP installed in the memory subsystem of a commodity microprocessor motherboard. In addition to the MAP, this figure also shows two standard DIMMs resident on the memory bus as well as the memory controller. This controller may be part of the Intel Northbridge or it may be part of the AMD microprocessor.
In looking at the MAP portion of the diagram, it can be seen that the memory bus is connected via a set of isolation switches to additional 1 to 4 Gbytes of SDRAM located on the MAP. During normal operation the microprocessor will see both the standard DIMMs and the memory located on the MAP as part of its memory pool.
It can therefore access all of this memory with equal ease. Typically the microprocessor will store data that it wants to share with the MAP in the memory located on the Series I MAP.
Once it is ready to allow the MAP to access that data the microprocessor signals embedded SNAP, and the isolation switches will be activated thus removing the on-board SDRAM from the memory bus of the microprocessor.
The MAP User logic can now access the on-board SDRAM while the microprocessor simultaneously accesses the remaining DIMM based SDRAM to perform parallel functions. At this time both the MAP and the microprocessor can sustain full memory bus bandwidth, thus doubling the total memory bandwidth.
In addition to the SDRAM, the Series I MAP also contains one 64 bit wide 4 Mbyte QDR SRAM On-Board Memory bank
(OBM). Since this is QDR memory it has separate read and write ports which will allow full speed support of stream based memory operations.
The User Logic is a Stratix II FPGA and is available in three size options. The EP2S180, EP2S130 or the EP2S90 are all available in the Series I MAP allowing the user to tailor the MAPs size and price based on the application.
As with all SRC products, the Series I MAP uses SRC’s Carte™ Programming Environment. Users can program the Series I using ANSI standard C or Fortran and produce applications that are software compatible with other SRC systems. For users who don’t already have standard Carte development licenses, SRC has created a special version of Carte, called
iCarte™, just to support Series I MAP based systems at a greatly reduced price point.
(Read more about iCarte)
MAPstations™ using the Series I MAP are available with either AMD or Intel microprocessors with run time systems priced between $17,000 and $19,000 including SRC’s Carte Run Time Environment. These MAPstations can either be used as stand alone workstations or as very powerful nodes in commodity interconnected clusters.
For
more information on SRC's Series I MAP modules or MAPstations,
please e-mail sales@srccomputers.com.
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iCarte™
Powerful
Economical Development Environment for the Series I MAP®
First introduced in 2002, SRC’s Carte™ has proven to be a very user-friendly ANSI standard high level language programming environment for use on all SRC systems. Its feature-rich nature allows the use of familiar standard programming constructs in a wide range of bandwidth and memory intensive applications.
However with the introduction of the Series I MAP, many of the memory access and interconnect options that Carte supports in other SRC systems are not applicable. To address this reduced feature requirement and desired lower price point, SRC has introduced iCarte.
iCarte has the same familiar look and feel of standard Carte but without support for features not present in the systems using the Series I MAP such as multiple User Logic chips and shared common memory. Both ANSI C and Fortran are supported in an identical fashion as with standard Carte.
The standard Carte debug environment remains including the ability to target other SRC MAP
types, such as the Series H, for comparison and evaluation purposes. This allows a programmer to write an application and then see how its performance on the Series I compares to that same code’s performance on any other SRC MAP without actually having access to those other MAP types.
Priced at just $5,000 for a perpetual development license, iCarte provides a very powerful, economical easy-to-use ANSI standard language development environment for the Series I MAP.
For
more information on iCarte, please e-mail sales@srccomputers.com.
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Series
H MAP®
Five New
Configurations to Fit Your Needs and Price
The Series H MAP is quite possibly the most powerful reconfigurable processor available today. Supporting 26.4 Gbytes/s of external bandwidth, 2 Gbytes of on-board shared common memory, sixteen 64 bit random SRAM accesses per clock and two of the largest FPGAs available, its general purpose compute capability sets the bar for reconfigurable computation. So much so that for some applications it may actually be overkill. As a result, the Series H MAP is now available in
five different optional configurations. The first of these configurations is the fully populated Series H MAP as shown in Figure 1 that will have all the features summarized above.
Series H MAP Block Diagram,
Figure 1
The
second configuration is intended for applications that do not make use of the full GPIO bandwidth. Examples of this would be applications that do not use MAP Chaining or do not use the GPIO to connect to external devices. In this case the customer can choose to eliminate half of the GPIO connectivity. This option is referred to as the Half GPIOX Option. All other features of the MAP remain the same as in the full featured version.
The
third configuration is targeted at applications that do not need all the GPIO connectivity and also do not need two User Logic FPGAs. This Option is referred to as the Half GPIOX Single User Logic Option and removes one User Logic chip from the MAP as well as half the GPIO connectivity.
The
fourth configuration combines the Half GPIOX Single User Logic Option and also removes half of the OBM banks. This option will delete 4 of the physical OBM chips resulting in a limit of eight random 64 bit reads per clock. This option is called the Half GPIOX Single User Logic Half OBM Option.
Finally the
fifth option starts with the Half GPIOX Single User Logic Half OBM option and also removes the on-board common memory. This is the least featured Series H MAP and is the Half GPIOX Single User Logic Half OBM no CM Option.
These five configurations combined with the Series I MAP offerings
provide a very broad software compatible continuum of performance with an equally broad set of price points. In addition, all of these Series H MAP offerings can be mixed in a single system providing customers a scalable reuse path.
For
more information on the new configurations of the Series H MAP, please e-mail
sales@srccomputers.com.
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