SRC® Code Development & Debugging Tools and
Optimization
CODE DEVELOPMENT TOOLS
The Carte™ Programming Environment supports co-development of programs written to run on microprocessors and FPGA-based MAP® processors. The MAP compiler compiles codes into configuration bit-streams that configure the MAP processor. The Intel compiler compiles codes for the microprocessor.
Code intended to be compiled for the MAP processor is written as separate subprograms and collected into a single logic block by the Carte Programming Environment through the code in-lining process. The subprograms are called from routines executing on the microprocessor, as well as from other MAP routines. This technique permits hierarchical code development and code reuse. It also permits expressing greater parallelism within code blocks and permits optimizations across subprogram boundaries. The Carte Programming Environment then provides support for integrating the microprocessor routines, MAP routines, and libraries into a single Unified Executable that contains the microprocessor instructions, MAP logic, and all required library routines to manage the control of the program.
DEBUGGING TOOLS
The Carte Programming Environment fully supports co-development of software and hardware functional units through the use of debugger and hardware simulation tools. With the Carte Programming Environment managing both the microprocessor code as well as the simulation code, applications execute seamlessly in hardware or simulation environments.
The SRC Carte Programming Environment creates program executables that support source-level debugging through the Intel® debugger, or any microprocessor-oriented code development tools.
In debugger mode, a program is executed entirely in the microprocessor. The routines coded for the MAP processor are source line unchanged but retargeted for the microprocessor. This mode of development permits highly productive algorithm development and debugging. A MAP routine that is developed using debugger mode will execute correctly when retargeted to the MAP processor.
Because the Carte Programming Environment creates executables that can be used in conjunction with Verilog/VHDL simulators such as VCS™ from Synopsys®, programmers who are developing algorithms that use application specific functional units (ASFs) written in Verilog or VHDL have additional debugging services available to them.
OPTIMIZING
Parallelism
The MAP compiler creates optimized logic for the MAP with performance being achieved through creation of pipelined logic blocks and concurrent execution of parallel logic blocks.
Code segments can be tagged as parallel or critical regions using SRC pragmas and directives. The MAP compiler performs data dependency analysis to provide optimized pipelines from code loops and is capable of optimizing the use of On-Board Memory to prevent loop slowdowns. All pipelined loops generate logic targeted to produce results at each clock cycle. However, the compiler is capable of adapting to data dependencies and adjusting the pipeline as is appropriate.
Managing the Memory Hierarchy
Function calls to Carte data prefetch routines permit the programmer to explicitly manage data movement into and out of the MAP processor. Data prefetch units permit fetching and storing data using complex striding, scatter/gather, and compressed data prefetch that can be synchronously or asynchronously controlled within a MAP routine.
A low-latency data streaming functional unit allows data to feed computation without storing into intermediate memory. Within a MAP routine, the programmer can explicitly allocate arrays to On-Board Memory Banks and on-chip dual ported Block RAM. Data movement is optimized by the MAP compiler to avoid load/store operations within the pipelined code blocks using data registers and wires created by the compiler.
Application Specific Functional (ASF) Units
The Carte Programming Environment provides functional units for the standard operators supported within the C and Fortran languages. These include arithmetic and logical operators, and math functions. Additionally, a user can add ASF units, invoking them as function calls within the MAP routine.
An ASF is written using a hardware definition language such as Verilog or VHDL and permits creation of optimized hardware that yields maximum performance. For example, non-standard floating point precision arithmetic functional units could be defined and used within the MAP routine as function calls.