SRC® Hardware Specifications

MAP® Processor Specifications

APM Processor Module Specifications

SNAP Interface Specifications

Hi-Bar®Network Switch Specifications

Multi-Ported Common Memory (MPCM) Specifications

 

MAP® Processor Specifications

  MAP Processor Series
H
Logic 

User Logic Chips

EP2S180

Control Logic Chip

EP2S130

Nominal Clock Rate (MHz)

150

Total User Logic Reconfiguration Time  (ms)

100
On-Board Memory (OBM)
# On-Board-Memory Banks - Logical 16

# On-Board-Memory Banks - Physical

8

Total OBM Bandwidth (BW)  (Gbytes/s)

19.2

OBM BW to User Logic  (Gbytes/s)

19.2

OBM BW to Control Logic  (Gbytes/s)

7.2

OBM Bank Width  (bits)

64

Total Simultaneous OBM Accesses 
(reads or writes)

16
Simultaneous User Logic OBM Accesses 
(reads or writes)
 
16

Total OBM Size  (Mbytes)

64

Bridge Port BW    (Gbytes/s)

4.8
On-Board Common Memory (OBCM) 

# On-Board-Memory Banks

2

Total OBM Bandwidth (BW)  (Gbytes/s)

8.4

OBM Bank Width  (bits)

64

Total Simultaneous OBM Accesses 
(reads or writes)

2

Total OBM Size  (Mbytes)

1024-2048
MAP Processor to System Interconnect

Sustained MAP Input Payload BW from System  (Gbytes/s)

7.2

Sustained MAP Output Payload BW to System  (Gbytes/s)

7.2

Simultaneous Sustained MAP Payload I/O BW to and from System    (Gbytes/s)

14.4
General Purpose I/O (GPIO)

Number of GPIO Ports per MAP Processor

1 or 2

GPIO Signal Level Standards

2.5VTTL/ LVDS

# Signal Paths per GPIO Port

96/48

Sustainable GPIO BW per Port  (Gbytes/s)

4.8/6.0

Maximum Data Rate per Signal Path  (Mbits/s)

600/1000

GPIO Interconnect Medium

User Determined
Physical Specifications

Power Supply Voltage

+12vdc

Maximum Power Consumption  (watts)

80

Form Factor

5.25

Cooling Methodology

Air

MTBF  (Khours)

195

  Series C, D, E, F, and G MAP processors are no longer available.  

  SRC Computers reserves the right to update these specifications at any time.

 

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APM Processor Specifications

CPU

Intel 1.6 GHz Atom Processor, Z530

    Front Side Bus

400 MHz

    Cache

L1 32 KB instruction / 24 KB data cache, 512 KB L2 advanced transfer cache

    FLOPS

2.92 GFLOPS theoretical peak performance (@1.46 GHz)

    CPU Memory

2 GB DDR2 400

    Memory Bandwidth

3.6 GB/s

Microprocessor-to-MAP® Processor Interconnect

Patented SNAP interconnect to the MAP processor

Interconnect payload bandwidth per port SNAP interconnect to MAP processor - TBD

Aggregate payload bandwidth between the SNAP interconnect and the MAP processor - TBD

Disk

One ESATA 150 (for external drive) with optional encryption capability

One 120 GB, 5400 RPM 1.8” SATA 150 non-encrypted hard drive

Either or both can be replaced with an Solid State Drive

External I/O

Serial

2- USB 2.0

Network

1-Gigabit Ethernet

Video

1-HDMI

Peripheral Cards Slot

1-XMC card slot (VITA 42.3, PCIe X1 lane)
1-SDHC card slot

MTBF (Khours)

TBD

Operating System

Fedora Linux

File Systems

ext3

Compilers

Intel C++, Intel Fortran, SRC Carte Programming Environment

Power

+12VDC (+2V/-1V), 20W Max

  SRC Computers reserves the right to update these specifications at any time.

 

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SNAP Interface Specifications

 

SNAP Interface Series

D

E

  SRC-7 Systems & Servers SRC-6 64 bit MAPstation Workstations, Systems & Servers
Port Configuration

# Input Ports

1

1

# Output Ports

1

1

Memory Bus Width  (bits)

144

144

Interleaved Memory Bus

Yes

Yes

SECDED Error Correction Code on Memory Bus

Yes  

Yes  

SECDED Error Correction Code

Yes

Yes

Bandwidth (BW)   

Interconnect Clock Rate  (MHz)

1000

100

# Signal Paths per Port

36

72

Maximum Data Rate per Signal Path  (Mb/s)

1000

200

Sustainable Payload BW per Port  (Gbytes/s)

3.6  

1.4  

Aggregate Sustainable I/O Port Payload BW  (Gbytes/s)

7.2

2.8

Memory Bus Clock Rate  (MHz)

133

133

Physical Specifications   

Maximum Power Consumption  (watts)

TBD

TBD

Form Factor

Pi  

Pi  

Interconnect Medium

Coax Ribbon

Coax Ribbon

Cooling Methodology

Air

Air

MTBF  (Khours)

97

97

   Series B and C SNAP Interfaces are no longer available.

   SRC Computers reserves the right to update these specifications at any time.

 

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Hi-Bar® Network Switch Specifications

 

Hi-Bar Series

  C

Port Configuration 

# Input Ports

16

# Output Ports

16
# Common Memory Ports 0

SECDED Error Correction Code

Yes

Bandwidth (BW) 

Nominal Clock Rate  (MHz)

166

# Signal Paths per Port

36

Maximum Data Rate per Signal Path    (Mb/s)

1000

Sustainable Payload BW per I/O Port    (Gbytes/s)

3.6

Aggregate Sustainable Payload BW  (Gbytes/s)

115.2

Physical Specifications

Power Supply Voltage

120vac

Maximum Power Consumption  (watts)

107

Form Factor

1U

Interconnect Medium

Coax Ribbon

Cooling Methodology

Air

MTBF  (Khours)

97.25

Series A and B Hi-Bar Switches are no longer available. The Series D Hi-Bar Switch is now called 
Multi-Ported Common Memory (MPCM) module. Please see the MPCM specifications below. 

SRC Computers reserves the right to update these specifications at any time.

 

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Multi-Ported Common Memory (MPCM) Specifications

Dimensions

1.75”H x 5.85”W x 9.5”D
(4.44  cm H x 14.86 cm W x 24.13 cm D)

# banks per MPCM module

2

DDR2 slots/bank

2

SDRAM volume per bank

16 Gbytes

I/O ports

4

Sustained DMA bandwidth per port

3.6 Gbytes/s

SRC Computers reserves the right to update these specifications at any time.

 

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