Patented Technology

SRC Computers holds fundamental U.S. and foreign patents covering hardware and software techniques for vastly accelerating data processing through the use of reconfigurable elements comprising one or more Direct Execution Logic blocks operating in conjunction with one or more commodity microprocessors.

 

SRC's patented technology, with filing dates back to 1997, also includes a number of general applications of Direct Execution Logic computing systems for parallelizing the execution of user-defined algorithms including acceleration of web site access and processing.

 

SRC has exclusive rights to the following patents:

 

Patent #	Patent Title
7,237,091	Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
7,225,324	Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions
7,197,575	Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
7,167,976	Interface for integrating reconfigurable processors into a general purpose computing system
7,155,708	Debugging and performance profiling using control data flow graph representations with reconfigurable hardware
7,155,602	Interface for integrating reconfigurable processors into a general purpose computing system
7,149,867	System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware
7,134,120	MAP compiler pipelined loop structure
7,124,211	System & method for explicit communication of messages between processes running on different nodes in a clustered multiprocessor system
7,003,593	Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port
6,996,656	System and method for providing an arbitrated memory bus in a hybrid computing system
6,983,456	Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
6,964,029	System and method for partitioning control-dataflow graph representations
6,961,841	Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
6,941,539	Efficiency of reconfigurable hardware
6,836,823	Bandwidth enhancement for uncached devices
6,781,226	Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
6,627,985	Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
6,594,736	System and method for semaphore and atomic operation management in a multiprocessor
6,434,687	System and method for accelerating web site access and processing utilizing a computer system incorporating reconfigurable processors operating under a single operating system image
6,356,983	System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
6,339,819	Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer
6,295,598	Split directory-based cache coherency technique for a multiprocessor computer system
6,247,110	Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
6,076,152	Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
6,026,459	System and method for dynamic priority conflict resolution in a multiprocessor computer system having shared memory resources