SRC Computers, Inc.: SRC White Papers

SRC White Papers

The following SRC and partner white papers are available upon request by emailing marketing@srccomputers.com. Please include your name and the name of your organization when requesting these documents.

Computed Tomography (CT) Scan Image Reconstruction on the SRC-7
The SRC-7 system architecture is well suited to accelerating of CT scan image reconstruction. In the simplest SRC-7 system implementation, a microprocessor is paired with a Series H MAP^® processor. These two processors working together achieve a 29x performance boost over the 3GHz 64-bit Xeon microprocessor working alone. This means that if a traditional computer takes 10 minutes to reconstruct a CT scan image, the SRC-7 system will take only 20 seconds to reconstruct the same image.

Algorithm Optimization Case Study - SAR Backprojection
The Spotlight Synthetic Aperture Radar (SAR) Backprojection algorithm is considered to be the “gold standard” of the SAR imaging techniques. This paper describes a study that compared the performance of a MATLAB implementation of a 2D SAR Backprojection application to a MATLAB – MAP implementation and to an all C Language implementation.

Algorithm Optimization Case Study - Edge Detection
This paper will discuss the use of various standard program optimization techniques as applied to an edge detection application written in C for use on the SRC-7 Series H MAP processor. The SRC-7 Series H MAP can yield more than two orders of magnitude performance improvements over a 3GHz Xeon microprocessor using Intel IPPLIB v5.1 image processing functions.

SRC MAPstation™ Image Processing: Two Dimensional Floating Point Fast Fourier Transforms
Using the complex floating point programmable FFT from SRC Computer’s image processing library, engineers have demonstrated a 2D FFT with a O(N) transpose operation. This means that every time image resolution grows by 2x, the image processing time grows by the same amount, thus allowing efficient and very high-resolution image processing in the frequency domain vs. traditional microprocessor methods. This O(N) transpose operation is achieved using the advanced memory architecture in SRC’s Series H MAP processor.

SRC MAPstation Image Processing: Intensity Histogram
Given the importance of the histogram operation, SRC recently developed a MAP histogram function specifically to support image applications. This paper will discuss this function as well as provide a detailed example of how to use the function in a MAP C program. Later papers will incorporate this simple function into real image applications and discuss realizable performance at the application level.

SRC Carte™ and Graphical User Interface (GUI) Programming
All capabilities available to the programmer under Linux remain available in the Carte Programming Environment. Since Carte generates a single integrated executable containing both CPU and MAP processor code, it is often easiest to utilize the Carte Makefile for heterogeneous compilation. This paper describes the development of a simple GTK based GUI application program within the Carte Programming Environment, with emphasis on the Makefile.

Introduction to the SRC-7 MAPstation

This paper provides a general overview of the system architecture, components, software, and performance of the SRC-7 MAPstation class of systems.

First Level Application Screening

This paper describes system level requirements that SRC systems tend to be very well oriented toward; application areas where SRC systems have already achieved at least an order of magnitude performance improvement at the application level; and generalized software application features that are typically found in applications that benefit from the use of SRC technology.

Black-Scholes Performance on the SRC-7

This paper describes SRC's implementation of a Black-Scholes double precision floating point algorithm on several of its MAP reconfigurable processors and the resulting speed-up compared to conventional microprocessor-based systems.

3D FFT Performance on the SRC-7

This paper discusses SRC's implementation of a 128x128x128 Complex Three-Dimensional Fast Fourier Transform with double precision floating point calculations on its new SRC-7 Series H MAP reconfigurable processor.

Designing and Using FPGAs in Double-Precision Floating-Point Math (Altera Corporation)

This paper demonstrates the double-precision floating-point performance of Altera FPGAs through both theoretical “paper and pencil” calculations and real-world results.

Floating-Point Compiler -- Increasing Performance With Fewer Resources (Altera Corpoation)

Showing new levels of high-performance, high-density, IEEE754-compliant floating-point applications in FPGAs is the focus of this white paper. In addition, a new tool is introduced that will allow 100 percent of the floating-point capability of the FPGA device to be used.

IMPLICIT+EXPLICIT™ Architecture

This paper explains SRC's innovative IMPLICIT+EXPLICIT architecture, which fully integrates Dense Logic Device (DLD) technology and reconfigurable Direct Execution Logic (DEL) with the Carte Programming Environment, delivering orders of magnitude increases in performance.

GPIOX Hardware Specifications

This paper defines all necessary parameters to allow third parties to successfully design GPIOX daughtercards for operation in conjunction with SRC's MAP processors.

3D Pre-stack Wave Equation Depth Migration

The author of this paper, David Caliga, SRC's Application Technology Manager, explains how SRC's MAP technology can accelerate processing time for compute-intensive floating point imaging such as the 3D Pre-stack Wave Equation Depth Migration (WEMIG).

Bandwidth Efficiency and Utilization Using Direct Execution Logic

In this paper, the authors state that the performance improvement trend in microprocessors has slowed, limiting bandwidth utilization and efficiency. The solution is to make Direct Execution Logic (DEL) available to programmers so they can take advantage of scalable locality mechanisms and computational resources, thereby achieving maximum possible bandwidth performance.

Search Algorithm Performance

David Caliga, SRC's Application Technology Manager, discusses how SRC's MAP processor technology can effect significant performance gains for applications such as database queries, internet searches, spam filters and bioinformatics computations.

Wavelet Versatility Benchmark

Dr. Wim Böhm and Dr. Jeff Hammes describe their research results in which they implement a wavelet image compression algorithm on the MAP-based SRC system and compare the performance of the SRC system to that of a microprocessor-based system.







	SRC White Papers The following SRC and partner white papers are available upon request by emailing marketing@srccomputers.com. Please include your name and the name of your organization when requesting these documents. Computed Tomography (CT) Scan Image Reconstruction on the SRC-7 The SRC-7 system architecture is well suited to accelerating of CT scan image reconstruction. In the simplest SRC-7 system implementation, a microprocessor is paired with a Series H MAP^® processor. These two processors working together achieve a 29x performance boost over the 3GHz 64-bit Xeon microprocessor working alone. This means that if a traditional computer takes 10 minutes to reconstruct a CT scan image, the SRC-7 system will take only 20 seconds to reconstruct the same image. Algorithm Optimization Case Study - SAR Backprojection The Spotlight Synthetic Aperture Radar (SAR) Backprojection algorithm is considered to be the “gold standard” of the SAR imaging techniques. This paper describes a study that compared the performance of a MATLAB implementation of a 2D SAR Backprojection application to a MATLAB – MAP implementation and to an all C Language implementation. Algorithm Optimization Case Study - Edge Detection This paper will discuss the use of various standard program optimization techniques as applied to an edge detection application written in C for use on the SRC-7 Series H MAP processor. The SRC-7 Series H MAP can yield more than two orders of magnitude performance improvements over a 3GHz Xeon microprocessor using Intel IPPLIB v5.1 image processing functions. SRC MAPstation™ Image Processing: Two Dimensional Floating Point Fast Fourier Transforms Using the complex floating point programmable FFT from SRC Computer’s image processing library, engineers have demonstrated a 2D FFT with a O(N) transpose operation. This means that every time image resolution grows by 2x, the image processing time grows by the same amount, thus allowing efficient and very high-resolution image processing in the frequency domain vs. traditional microprocessor methods. This O(N) transpose operation is achieved using the advanced memory architecture in SRC’s Series H MAP processor. SRC MAPstation Image Processing: Intensity Histogram Given the importance of the histogram operation, SRC recently developed a MAP histogram function specifically to support image applications. This paper will discuss this function as well as provide a detailed example of how to use the function in a MAP C program. Later papers will incorporate this simple function into real image applications and discuss realizable performance at the application level. SRC Carte™ and Graphical User Interface (GUI) Programming All capabilities available to the programmer under Linux remain available in the Carte Programming Environment. Since Carte generates a single integrated executable containing both CPU and MAP processor code, it is often easiest to utilize the Carte Makefile for heterogeneous compilation. This paper describes the development of a simple GTK based GUI application program within the Carte Programming Environment, with emphasis on the Makefile. Introduction to the SRC-7 MAPstation This paper provides a general overview of the system architecture, components, software, and performance of the SRC-7 MAPstation class of systems. First Level Application Screening This paper describes system level requirements that SRC systems tend to be very well oriented toward; application areas where SRC systems have already achieved at least an order of magnitude performance improvement at the application level; and generalized software application features that are typically found in applications that benefit from the use of SRC technology. Black-Scholes Performance on the SRC-7 This paper describes SRC's implementation of a Black-Scholes double precision floating point algorithm on several of its MAP reconfigurable processors and the resulting speed-up compared to conventional microprocessor-based systems. 3D FFT Performance on the SRC-7 This paper discusses SRC's implementation of a 128x128x128 Complex Three-Dimensional Fast Fourier Transform with double precision floating point calculations on its new SRC-7 Series H MAP reconfigurable processor. Designing and Using FPGAs in Double-Precision Floating-Point Math (Altera Corporation) This paper demonstrates the double-precision floating-point performance of Altera FPGAs through both theoretical “paper and pencil” calculations and real-world results. Floating-Point Compiler -- Increasing Performance With Fewer Resources (Altera Corpoation) Showing new levels of high-performance, high-density, IEEE754-compliant floating-point applications in FPGAs is the focus of this white paper. In addition, a new tool is introduced that will allow 100 percent of the floating-point capability of the FPGA device to be used. IMPLICIT+EXPLICIT™ Architecture This paper explains SRC's innovative IMPLICIT+EXPLICIT architecture, which fully integrates Dense Logic Device (DLD) technology and reconfigurable Direct Execution Logic (DEL) with the Carte Programming Environment, delivering orders of magnitude increases in performance. GPIOX Hardware Specifications This paper defines all necessary parameters to allow third parties to successfully design GPIOX daughtercards for operation in conjunction with SRC's MAP processors. 3D Pre-stack Wave Equation Depth Migration The author of this paper, David Caliga, SRC's Application Technology Manager, explains how SRC's MAP technology can accelerate processing time for compute-intensive floating point imaging such as the 3D Pre-stack Wave Equation Depth Migration (WEMIG). Bandwidth Efficiency and Utilization Using Direct Execution Logic In this paper, the authors state that the performance improvement trend in microprocessors has slowed, limiting bandwidth utilization and efficiency. The solution is to make Direct Execution Logic (DEL) available to programmers so they can take advantage of scalable locality mechanisms and computational resources, thereby achieving maximum possible bandwidth performance. Search Algorithm Performance David Caliga, SRC's Application Technology Manager, discusses how SRC's MAP processor technology can effect significant performance gains for applications such as database queries, internet searches, spam filters and bioinformatics computations. Wavelet Versatility Benchmark Dr. Wim Böhm and Dr. Jeff Hammes describe their research results in which they implement a wavelet image compression algorithm on the MAP-based SRC system and compare the performance of the SRC system to that of a microprocessor-based system.



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